The present application relates generally to the manufacturing of electronic circuits and systems, and more specifically to a system and method of achieving improved test and configuration throughput of electronic circuits (e.g., integrated circuits (ICs)), printed circuit boards (PCBs), and electronic sub-assemblies and systems. The presently disclosed system and method employ a tester resource (e.g., a computer and controller) that uses a parallel test architecture. Further, the disclosed system and method are operative to calculate an optimal number of units (e.g., ICs or PCBs) to test and/or configure in parallel, thereby allowing manufacturers to achieve both maximum test and configuration throughput and maximum utilization of the tester resource.
In recent years, there has been a significant increase in the cost of testing and configuring electronic circuits and systems. One factor contributing to the higher test and configuration costs is the increased use of programmable memories such as FLASH, and programmable logic devices such as Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs). Another contributing factor is the increased size and complexity of these programmable devices. These factors have resulted in an increased amount of configuration data, which is typically programmed into ICs, PCBs, and electronic systems during manufacturing. As a result, the time required to program such configuration data has increased, thereby increasing manufacturing and end-product costs, which are typically passed along to the customer.
Still another factor contributing to higher product costs is the continuing increase in manufacturing test times. Electronic products are normally tested following fabrication and assembly to assure that no defects have been introduced into the manufacturing process. As such electronic products have continued to offer more features, higher performance, and reduced size, the ICs and PCBs used to make these products have become more complex and more highly integrated. This has resulted in increased amounts of test data and increased manufacturing test times, which have further increased manufacturing and end-product costs.
Test and configuration of ICs, PCBs and electronic sub-assemblies and systems are typically automated to facilitate production manufacturing. Such automation, in the form of Automated Test Equipment (ATE) and automated handlers for the units under test (UUTs), speeds production and reduces labor costs. For example, UUTs such as packaged ICs and PCBs may employ ATE and automated handlers during the manufacturing process. Each ATE typically employs a dedicated handler that automatically loads a UUT into a test fixture on the ATE, which then tests and/or configures the UUT. After the UUT is tested and configured, the automated handler unloads the UUT from the ATE, and loads a new UUT into the ATE test fixture for subsequent testing and configuration. The handler-tester pair, often referred to as a test cell, continues this process of loading, testing/configuring, and unloading the UUTs. The time required for the handler to manipulate the UUTs for test/configuration, i.e., for loading and unloading the UUTs, is typically referred to as the “index time”.
The time required for the automated handler to sort the UUTs that have failed testing from those that have passed is known as the “sort time”. The sorting process frequently merely involves marking the failing UUTs. For example, during wafer testing, a failing die may be marked with an ink dot. In other sorting techniques, the test cell may “map” the pass/fail results, and log the map onto a computer for subsequent sorting off-line. Accordingly, the sort time is generally insignificant when compared to the index, test, or configuration times, as it can be easily masked so that the throughput of the manufacturing line and the tester utilization are not unduly impacted by the sorting method.
Even with automated handlers and testers, manufacturers often employ additional techniques to improve test and configuration throughput including ganged test and configuration and multi-site testing, in which multiple UUTs are tested and configured in parallel. In this way, multiple UUTs can be tested and configured in the same amount of time as a single unit, thereby reducing the effective per-unit test/configuration times. Such techniques can improve throughput, especially when the index times are significantly shorter than the per-unit test and configuration times. However, merely increasing the number of UUTs that are tested and configured in parallel is not always enough to achieve a desired level of throughput, even when massively parallel testing techniques are employed. Further, parallel testing alone does not always result in the maximum achievable level of throughput. Moreover, conventional parallel testing techniques are often prohibitive in terms of cost.
Although conventional testers can be used for ganged and multi-site test and configuration, such testers are typically limited in the number of units that can be tested and configured in parallel. Such limitations are inherent in the tester's architecture, which depends on individual tester channels and the pattern memory associated with these channels to provide the parallelism required for multi-site testing. Because the channels and memory are limited in number and capacity in these tester architectures, there is a limit to the number of units that can be tested or configured simultaneously. Depending on the requirements of the UUT and the limitations of the tester, conventional testers are typically capable of testing only from 2 to 1024 units in parallel. As such, conventional tester architectures are not readily scalable for parallel testing, and so their costs often rise prohibitively as the requirements for parallelism and tester resources increase.
FIG. 1a depicts a conventional ATE or personal computer (PC) system 100a configured to perform ganged test and configuration. As shown in FIG. 1a, there are 4 UUTs 106.1-106.4 connected to a single ATE or personal computer (PC) 102. Each one of the UUTs 106.1-106.4 is of the same type, i.e., they are identical circuits (ICs or PCBs) with respect to their design and intended functionality, and each UUT 106.1-106.4 has the same number of inputs and outputs. In the ganged configuration, each one of the UUT inputs IN0, IN1, IN2, and IN3 is bused and sourced from the ATE or PC 102. The ATE or PC system 100a therefore supplies outputs corresponding to the IN0, IN1, IN2, and IN3 inputs, which connect to the respective IN0, IN1, IN2, and IN3 inputs of the UUTs 106.1-106.4. The ATE or PC 102 therefore provides input data to each one of the four UUTs 106.1-106.4 simultaneously such that all of the UUTs receive the same test data as inputs. This bused configuration for the inputs of the UUTs 106.1-106.4 provides the benefit of requiring fewer tester channels to control the inputs of the UUTs. However, there is a drawback in that an individual UUT cannot receive test data separate from the other UUTs 106.1-106.4. For example, if unique serial numbers need to be programmed into each one of the UUTs 106.1-106.4, this would not be possible with the ganged test configuration 100a of FIG. 1a. 
To allow one of the UUTs 106.1-106.4 to receive test data separately from the other UUTs 106.1-106.4, the individual inputs of each UUT would normally have to be controlled by discrete tester channels, as depicted in the multi-site test configuration 100b of FIG. 1b. However, because PCBs and ICs may have hundreds or even thousands of inputs and outputs, the number of inputs/outputs may rapidly exceed the number of tester channels available, even for relatively small numbers of UUTs. A further consideration when using either of the above-described approaches of FIGS. 1a-1b is that the ATE or PC 102 is capable of driving only a limited number of loads (i.e., UUTs) due to drive limitations of the tester pin electronics. As such, the ganged test and multi-site test configurations 100a-100b of FIGS. 1a-1b are not readily expandable, and so it is typical that only a relatively small, limited number of UUTs can be tested and configured in parallel with these tester configurations.
FIGS. 1a-1b also depict the connections from the outputs of the UUTs 106.1-106.4 to the ATE or PC 102 for ganged test and multi-site test, respectively. As shown in FIGS. 1a-1b, the UUT outputs are not bused, but rather they are individually connected to a single tester channel of the ATE or PC 102. Multiple outputs cannot be connected together, as there would be contention should the outputs drive opposite logic values. In addition, connecting each output back to the ATE or PC 102 individually enables the tester to check the response of each UUT during test or configuration, and to determine which UUTs 106.1-106.4 have passed or failed testing/configuration. A dedicated output line back to the ATE or PC 102 for each output of every UUT is therefore required. In the testers of FIGS. 1a-1b, each UUT has one output, and there are four UUTs. Four tester channels are therefore used on the ATE or PC 102. As a result, for conventional ganged test and multi-site test configurations, the number of output signals connected from the UUTs back to the ATE or PC can be very large, depending on the number of UUTs and the number of outputs per UUT. For example, given eight UUTs, each having 200 outputs, 1600 separate tester channels on the ATE or PC 102 would be required to perform the ganged or multi-site testing.
It is noted that test configurations such as those depicted in FIGS. 1a-1b are also possible by configuring multiple testheads on a single ATE (typically no more than 4 testheads) operating asynchronously. However, this can be a costly approach to expanding the tester, and there is still a limit to the number of parallel sites that can be configured for a particular type of UUT.
Although there are alternative ways that ganged and multi-site testing can be configured and performed, these alternative approaches also have limitations in the number of UUTs that can be tested and configured simultaneously. This is primarily due to considerations for connecting the UUT inputs and outputs to the ATE or PC. Such limitations are typically inherent in the ATE architectures and the approaches used. Further, the number of UUTs that can be tested simultaneously using conventional ATE is often relatively small in number. Consequently, with these conventional approaches, the number of UUTs that can be handled, tested, and configured in parallel is generally dictated by the limitations of the ATE or PC system, and not the requirements for test and configuration throughput.
FIG. 2 depicts another conventional parallel test system 200, which uses a distributed network such as a computer network 210 (e.g., Ethernet) to network together a number of ATEs via the console workstations of the testers 212.1-212.5. As shown in FIG. 2, a computer 202 on the network is used to provide a centralized test supervisor/monitor. This arrangement provides for a parallel test and configuration environment with multiple/independent tester resources (ATEs) and expandable bandwidth, in which the independent tester resources operate asynchronously to one another. However, expansion using the approach of FIG. 2 can be costly because it typically requires the addition of one or more ATEs and ATE consoles.
Another consideration involves the handling techniques employed, and how they affect throughput when combined with parallel testing. For example, with multi-site testing, multiple UUTs are typically handled in parallel as a group, as opposed to handling each UUT sequentially. With multiple UUTs handled in parallel, it effectively reduces the per-unit handling time. Although the combined handling time for handling multiple UUTs simultaneously (i.e., in parallel or as a group) often takes longer then handling a single UUT sequentially, the effective index time per UUT is still reduced. As a result, when the test time is significantly greater than the index time, handling multiple UUTs as a group essentially masks some of the indexing time. For example, during wafer test, multiple die may be indexed simultaneously. In this case, the handler probes multiple die on the wafer and the ATE tests these multiple sites simultaneously, thereby reducing both the per-unit index time and per-unit test time that would otherwise be incurred by handling and testing one die at a time. Techniques for racking PCBs so that multiple boards can be handling simultaneously may also be employed.
Still another conventional handling technique involves handling one UUT while another UUT is being tested. This approach has been used for PCB testing and is often referred to as “dual well” testing, typically with “left” and “right” wells, as the test fixtures are designed with two wells for accepting one PCB, i.e., “PCB left”, while the other PCB, i.e., “PCB right”, is being tested. When “PCB right” finishes its test, the test for “PCB left” begins automatically, and the tested “PCB right” is removed and a new PCB is inserted in the “right” well. However, this approach does not use parallel testing, and typically does not provide for an optimal level of throughput. Dual well testing only affects the overall throughput by reducing the handling time for removing a tested PCB and inserting another PCB. Overall test times are not reduced. Dual well fixtures are sometimes designed such that the wells are wired together when the test channels needed for the PCB exceed more than half of the ATE test channel resources. In this case, there are “shared” wires between the ATE and the fixture well. Such an arrangement may contribute to signal integrity problems in the test environment, especially when testing high-speed signals on the PCBs.
Accordingly, the conventional techniques described above for providing test and/or configuration of ICs, PCBs, and electronic sub-assemblies and systems are generally incapable of providing an optimal or maximum achievable level of throughput. Although this is due at least in part to the limitations of the ATE or PC system, it is primarily due to the misconception that simply increasing the number of UUTs tested and configured in parallel will result in an increased throughput. With conventional approaches, the test/configuration time and/or the handling time are not fully masked in the test cell, and therefore the throughput is reduced. With a single tester resource, there is little flexibility in adjusting the handling or determining the number of UUTs that can be tested and configured in parallel. This is because the throughputs are typically dictated by cost and resource limitations of the ATE, e.g., the number of available tester channels compared to the number of pins per die required for configuration and test. Increasing the number of tester-handler pairs may achieve a higher overall throughput, when considering a combination of multiple test cells. However, this approach can be prohibitive given the costs of adding such expensive capital equipment to a manufacturing line.
It would therefore be desirable to have an improved, low cost system and method of testing and configuring electronic circuits and systems that may be employed to obtain an optimal or maximum achievable throughput of test and configuration for ICs, PCBs, and any other suitable electronic sub-assembly or system, while avoiding the drawbacks of the above-described conventional approaches.